1. Field of the Disclosure
The present disclosure generally relates to data processors, and more particularly to error protection for data processors.
2. Description of the Related Art
A data processor typically employs an instruction pipeline to execute instructions. Each instruction requires one or more pipeline resources, such as registers in a register file, entries in a reorder buffer or load/store queue, and the like, in order to execute. Accordingly, a portion of the instruction pipeline, such as the dispatch unit, is typically employed to dedicate, on a temporary basis, pipeline resources to an instruction. However, data corruption at the data processor, such as data corruption resulting from soft errors, can cause an architectural state error, whereby an instruction incorrectly accesses a resource assigned to a different instruction. Architectural state errors can be addressed by conventional error detection techniques, such as the use of error correcting codes (ECC) or redundant execution of each instruction. However, such techniques can have an undesirable impact on performance.
The use of the same reference symbols in different drawings indicates similar or identical items.